Many integrated circuit (IC) manufacturing processes require a minimum metal density for the metal interconnections on each layer of a multi-layer IC chip design. For instance, Chemical Mechanical Polishing (CMP) is often a step of the chip manufacturing process that requires a uniform distribution of metal and silicon over the surface of the chip to achieve the desire degree of planarization.
After making a detailed routing design, however, there are often areas on a chip where the minimum metal density requirement for the metal interconnects is still not met. To remedy this, the current approach is to add extra metal (dummy metal objects) as part of the metal fill procedures. Unfortunately, the current approaches, while taking into account the density requirements, do not account for the impact that dummy metal object placement has on the timing aspects of individual electrical signal networks (nets) in a circuit design.